1. Field of the invention
The present invention relates to a semiconductor device and a method of controlling the semiconductor device.
2. Description of the Related Art
NAND flash memories and AND flash memories are widely used as flash memories for storing data. Examples of NAND flash memories that have floating gates (FG) as charge accumulation layers are disclosed in Japanese Unexamined Patent Publication No. 2001-308209 and Japanese Laid-Open Patent Application No. 2001-518696.
FIG. 1 illustrates the array structure of a conventional FG-type NAND flash memory. In FIG. 1, WL000 through WL031 indicate word lines that are provided for one unit block, BLm indicates bit lines, and M indicates memory cells. The bit lines BLm are connected to page buffers 100 through 10m. Every thirty-two memory cells M are connected in series so as to form one memory cell string for each bit line BLm in each one unit block. One end of each of the memory cell strings M000 through M031, . . . , Mm00 through Mm31 is connected to an array Vss line ARVSS via select source gates SSG00 through SSG0m corresponding to the potential of a select line SSG0. The other end of each of the memory cell strings M000 through M031, . . . , Mm00 through Mm31 is connected to the bit lines BL0 through BLm via select drain gates SDG00 through SDG0m and drain contacts 220 through 22m corresponding to the potential of a select line SDG0. A desired block is selected by controlling the select gate based on an address signal, and the other blocks remain unselected. The memory cells connected to each one unit in each block form one group (a memory cell group).
FIG. 2 is a cross-sectional view of a conventional FG-type NAND flash memory. In FIG. 2, memory cells are denoted by M, the bit line is denoted by BL, the select source gate is denoted by SSG, the select drain gate is denoted by SDG, a source diffusion layer is denoted by 11, a diffusion layer is denoted by 12, a drain diffusion layer 13 is denoted by 13, and a drain contact is denoted by 22. The line width of the select drain gate SDG is denoted by W_SDG, the line width of each memory cell M is denoted by W_WL, the gap between the select line SDGn and the adjacent word line WL is denoted by S_SDG-WL, and the gap between each two neighboring word lines is denoted by S_WL-WL. The relationship between the select drain gate SDG and the line width of each memory cell is expressed as W_SDG>W_WL. The relationship between the gap between the select line SDGn and the adjacent word line WL and the gap between each two neighboring word lines WL is expressed as S_SDG-WL>S_WL-WL.
FIG. 3A is a cross-sectional view of a cell of the FG-type NAND flash memory, and FIG. 3B is a cross-sectional view of a select gate. As shown in FIG. 3A, the memory cell M has a structure in which a tunnel oxide film 32, a polycrystalline silicon floating gate 33, an oxide film 34, a nitride film 35, an oxide film 36, and a control gate 37 are stacked in this order on a silicon substrate 31. As shown in FIG. 3B, the select gates SSG and SDG each have a structure in which an oxide film 42 and a gate electrode 43 are stacked in this order on a silicon substrate 41. Here, the relationship between the line width of each memory cell M W_WL and each line width of the select gates SSG and SDG is expressed as W_WL<W_SSG, W_SDG. Each of the line widths W_SSG and W_SDG is greater than the line width of each memory cell M W_WL, so that leakage can be prevented in the gate portion at the time of reading or programming. Also, the gap S_SDG-WL between the select gate and the adjacent word line is greater than the gap between each two neighboring word lines S_WL-WL, so that all the word lines WL have the same widths when being processed.
FIG. 4 shows the Vt distribution of the FG-type NAND flash memory. In an erasing state (data 1), the threshold value of a FG-type NAND flash memory cell is set to a negative value. In a writing state (data 0), the threshold value of a FG-type NAND flash memory cell is set to a positive value.
In recent years, NAND flash memories of a SONOS (semiconductor-oxide-nitride-oxide-semiconductor) type have been developed. A SONOS-type NAND flash memory stores information, using a nitride film as a charge accumulation layer, instead of a floating gate. This technique is disclosed in Japanese Unexamined Patent Publication No. 2003-204000. In a non-volatile semiconductor memory having a SONOS structure, multi-value information can be held by performing charge injection into a gate insulating film from the source side or the drain side.
In a conventional NAND cell array, blocks (erasing units) are divided using select gates, and various operations are performed with a selected one of the blocks. The unselected blocks are prevented from disturbance caused by the selected block.
However, as higher integration and lower voltages are being achieved, leakage current caused in unselected blocks at the time of reading or programming has become a problem, as accurate reading cannot be performed. Also, a core cell array has each one NAND string formed with thirty-two cells for higher integration these days. However, in a SONOS-type NAND flash memory, it is preferable to form a core cell array with sixteen cells, so as to reduce adverse influence of disturbance. In such a case, the number of drain contacts and source diffusion lines, as well as the number of select gates, becomes larger with respect to the memory cell region, compared with a conventional case. As a result, the entire device region becomes larger. Particularly, as illustrated in FIGS. 2 and 3, the line widths of the conventional select gates SDG and SSG are greater than the line widths of the memory cells. Therefore, the circuit size cannot be reduced as the number of select gates becomes greater.